1. Field of the Invention
The invention relates to a line decoder integrated circuit for a memory working at low supply voltages.
2. Discussion of the Related Art
A line decoder is used notably for the selection or deselection of memory lines organized in matrix form. The term "selection" or "deselection" of a line is understood to mean the fact of imposing a certain voltage on this line. In formal terms, this implies a binary state that can therefore be symbolized by a logic 1 or a logic 0. In practice, it is usually understood that the selection of a line means carrying it to a certain positive potential (logic 1) and that the deselection means carrying it to a ground potential (logic 0). However, the value of the positive potential may differ according to whether the line is selected to read the state of a cell or to write a state therein.
The memories generally comprise several thousands of lines. When it is sought to select a cell of these memories, a word line and bit line are selected, the intersection of these lines corresponding to the cell. If a memory has, for example, a total of 2048 lines, these lines can be addressed with a word address comprising 11 bits that are referenced, for example, A10 to A0. In order to facilitate fast access to these lines, the memory is generally divided into blocks of lines. When a line has to be accessed the block that contains this line is accessed first. For example, a 2048-line memory can be divided into eight blocks of 256 lines.
To make it easy to decode line addresses to be selected or deselected, these blocks can be further sub-divided into sub-blocks, and so on and so forth. For example, it is possible to define a variable M representing the bits A10 to A8, a variable L representing the bits A7 to A4 and a variable P representing the bits A3 to A0. Thus, it can be shown that the time taken to gain access to the line to be selected is accelerated.
Since the variable M represents three bits, the lines of the memory can be grouped into eight blocks of 256 lines corresponding to the eight possible values of M (M0 to M7). Similarly, since the variable L represents four bits, the 16 possible values of L (L0 to L15) make it possible to determine 16 sub-blocks of 16 lines for each of the 8 blocks. Finally, the 16 possible values of P (P0 to P15) can be used to determine the 16 lines of the sub-block. Thus, each line will correspond to a triplet of variables M, L, P.
Since the lines are generally long, it is sometimes desirable to select only one part of a line. This makes it possible to take steps to counter the capacitive effects that delay the time needed for gaining access to the cells. For example, the lines are divided into two sectors. It is then enough to determine an additional sector variable N corresponding to a bit that takes one of two values N0 and N1. Thus, 4096 half lines corresponding to 2048 lines will be encoded. In practice, a line decoder of a memory array is placed in the middle of the memory array, defining right-hand and left-hand sectors or top and bottom sectors.
In the prior art, there is a known type of line decoder circuit such as shown at 70 in FIG. 5. This type of line decoder circuit comprises, for each line, a decoder circuit 72 or 74 including an input terminal 20 to receive a binary selection signal that typically comes from a NAND gate 22, supplied for all decoder circuits 72, 74, with several inputs. In the configuration described here above, there would be, for example, a three-input NAND gate corresponding to a triplet of values of the variables (N,M, L) defining a given block, sub-block and sector. Thus, a NAND gate 22 would be connected to 16 lines of a given sub-block, in a given sector. There would be 16 NAND gates per block, giving 128 NAND gates for the sector and 256 NAND gates for the entire memory. For a given sub-block of a given sector, these 16 lines will each be defined by a variable P value (P0 to P15).
For a given line, the input terminal 20 is connected to a selection transistor 24 between this input terminal and an inverter 26 whose output is connected to the line that is selected or deselected by this line decoder.
The selection transistor 24 is, for example, an N type transistor. Its drain 25 is connected to the input terminal 20. The control gate 28 of this transistor is connected to a selection voltage terminal 30 and its source 32 is connected to the input 34 of an inverter 26. This inverter 26 has two transistors 36 and 38, which are respectively P (38) and N (36)-type transistors that are series-connected between a line supply terminal 40 and a ground terminal 42. The output 44 of the inverter 26, constituted by the drains 46 of the two transistors 36 and 38 connected to each other, is connected to the line associated with the line decoder. The line supply terminal 40 gives the voltage desired at the line when it is selected, namely the read voltage or write voltage or any other voltage. The line supply terminal 40 therefore gives a potential corresponding to the selection logic 1 level. The potential corresponding to the deselection logic 0 level will be given by the ground terminal 42. The magnitude of the line supply voltage varies according to the technology used to make the memory of which the line forms a part.
The input 34 of the inverter 26, formed by the control gates 47 and 48 of the two transistors 36 and 38 connected to each other, is also connected to the drain 50 of a P type transistor 52 whose source 54 is connected to the line supply terminal 40 and whose control gate 56 is connected to the output 44 of the inverter 26.
Let us consider, for example, a line corresponding to a quadruplet of values (Na, Mb, Lc, Pd) of the variables (N, M, L, P) where a is an integer ranging from 0 to 2, b is an integer ranging from 0 to 7 and c and d as integers ranging from 0 to 15.
If it is desired to select this line and carry it thus to the potential of the line supply terminal 40, it is enough to form the address bit on 12 bits corresponding to the quadruplet of values Na, Mb, Lc and Pd. The signals applied to the line decoder circuit and corresponding to the variables N, M, L, P will then go to the logic 1 state. The selection transistor 24 is then on and the output of the NAND gate 22 is in the logic 0 state (in practice, the ground potential). The inverter 26 thus takes the line to the desired potential by means of its P type transistor 38.
If the line is to be deselected, it is enough for one of the values of the variables N, M, L or P to be different. The signal corresponding to this variable will thus go to the logic 0 state. The line in question is then connected to the ground by means of the N type transistor 36 of the inverter.
In practice, it is possible to reserve a quadruplet of values of the variables N, M, L, P for the deselection of all the lines of the memory. Thus, the deselection of a line by the changing of the address formed will not give rise to the selection of another line corresponding to the new address. It is also possible to add an additional address bit whose value would determine whether the operation to be carried out is a selection or a deselection.
To enable the testing of the cells of the memory array, the method generally used is that of adding on an N type insulation transistor 58 in series with the selection transistor 24. The control gate 60 of this transistor 58 is connected to the line supply terminal 40. Thus, during tests, the line supply voltage can be made to drop without any risk of short-circuiting this supply with the positive supply of the NAND gates. Indeed, the cells of certain non-volatile memories require high control voltages of 10 volts for example. A distinction is therefore made between the line supply voltage that may be present on the line and the selection voltages. For example, the logic circuits such as the NAND gates are typically supplied at a voltage of the order on five volts.
This type of circuit does not always work properly at a low input voltage. Nonetheless, it is increasingly being sought to obtain products with low selection voltages, on the order of three volts for example.
The improper operation of the type of line decoder described above is due to the presence of the selection transistor 24 which induces losses between the input terminal 20 and the input of the inverter due to the threshold voltage of this transistor. If the selection transistor is an enhanced type of transistor, its threshold voltage is typically on the order of one volt or even more, depending on the substrate effect. This higher threshold voltage causes problems in controlling the N-type transistor of the inverter. In particular, line deselection time increases substantially and it may actually become impossible to control the N-type transistor of the inverter at all.
The use of a selection transistor without implantation, known as a native or natural transistor, could be used to solve this problem. This type of transistor has a low threshold voltage of the order on 0.1 to 0.4 volts. However, this approach would necessitate a procedure for certifying this type of technology, and this is a particularly lengthy and costly procedure. It is also possible to solve this problem by increasing the selection voltage by pumping. This approach has the drawback of requiring additional circuits, which entails losses in terms of space required, consumption and reliability.
In the light of the above, one general aim of the present invention is to propose a line decoder circuit capable of working for low selection voltages without calling for pumping at these voltages.